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authorMarcelina Koƛcielnicka <mwk@0x04.net>2022-05-06 16:30:56 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2022-05-18 17:32:56 +0200
commit982a11c709b4b363f85ae52a127f8a98bda30a3f (patch)
treede2dd78747314064b3a7731fc4791b0ec7bfb77d /tests/memlib/memlib_lut.v
parent2a2dc12eb69f2e904609e5b8275ec885e21ecd26 (diff)
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Add memory_libmap tests.
Diffstat (limited to 'tests/memlib/memlib_lut.v')
-rw-r--r--tests/memlib/memlib_lut.v30
1 files changed, 30 insertions, 0 deletions
diff --git a/tests/memlib/memlib_lut.v b/tests/memlib/memlib_lut.v
new file mode 100644
index 000000000..1f20a110a
--- /dev/null
+++ b/tests/memlib/memlib_lut.v
@@ -0,0 +1,30 @@
+module RAM_LUT(
+ input [3:0] PORT_R_ADDR,
+ input [3:0] PORT_RW_ADDR,
+ input PORT_RW_CLK,
+ input PORT_RW_WR_EN,
+ input [3:0] PORT_RW_WR_DATA,
+ output [3:0] PORT_R_RD_DATA,
+ output [3:0] PORT_RW_RD_DATA
+);
+
+parameter INIT = 0;
+parameter PORT_RW_CLK_POL = 1;
+
+reg [3:0] mem [0:15];
+
+integer i;
+initial
+ for (i = 0; i < 16; i += 1)
+ mem[i] = INIT[i*4+:4];
+
+assign PORT_R_RD_DATA = mem[PORT_R_ADDR];
+assign PORT_RW_RD_DATA = mem[PORT_RW_ADDR];
+
+wire CLK = PORT_RW_CLK ~^ PORT_RW_CLK_POL;
+
+always @(posedge CLK)
+ if (PORT_RW_WR_EN)
+ mem[PORT_RW_ADDR] <= PORT_RW_WR_DATA;
+
+endmodule