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| author | N. Engelhardt <nak@yosyshq.com> | 2023-02-20 18:27:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-20 18:27:24 +0100 |
| commit | c8966722d2fcbff67a2724f921a3692ab63d83ec (patch) | |
| tree | 28ebdac931b3e2614d8d82c9c3ec623b9e553dd5 /tests/memlib/memlib_multilut.txt | |
| parent | f0116330bce4e787dcbbf81c6e901a44715589a8 (diff) | |
| parent | f80920bd9f1b235693d61427d1532b8465fce12c (diff) | |
| download | yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.tar.gz yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.tar.bz2 yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.zip | |
Merge pull request #3403 from KrystalDelusion/mem-tests
Diffstat (limited to 'tests/memlib/memlib_multilut.txt')
| -rw-r--r-- | tests/memlib/memlib_multilut.txt | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/memlib/memlib_multilut.txt b/tests/memlib/memlib_multilut.txt new file mode 100644 index 000000000..387f4f8e2 --- /dev/null +++ b/tests/memlib/memlib_multilut.txt @@ -0,0 +1,19 @@ +ram distributed \LUT_MULTI { + abits 4; + width 2; + init any; + port arsw "RW" { + clock posedge; + } + ifdef PORTS_QUAD { + option "PORTS" "QUAD" { + port ar "R0" "R1" "R2" { + } + } + } else ifdef PORTS_OCT { + option "PORTS" "OCT" { + port ar "R0" "R1" "R2" "R3" "R4" "R5" "R6" { + } + } + } +} |