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| author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-07-07 10:22:14 +1200 |
|---|---|---|
| committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2023-02-21 05:23:14 +1300 |
| commit | 48f4e0920291c3163ac9d987a62bdc6deed722f6 (patch) | |
| tree | 541ba4e503533bdc4e276ae2e71bc8b7dd9c5698 /tests/memlib/memlib_multilut.v | |
| parent | ac5fa9a83883ede45fac38c7288f8ade1887ade5 (diff) | |
| download | yosys-48f4e0920291c3163ac9d987a62bdc6deed722f6.tar.gz yosys-48f4e0920291c3163ac9d987a62bdc6deed722f6.tar.bz2 yosys-48f4e0920291c3163ac9d987a62bdc6deed722f6.zip | |
Asymmetric port ram tests with Xilinx
Uses verilog code from User Guide 901 (2021.1)
Diffstat (limited to 'tests/memlib/memlib_multilut.v')
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