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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-06 16:30:56 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 982a11c709b4b363f85ae52a127f8a98bda30a3f (patch) | |
| tree | de2dd78747314064b3a7731fc4791b0ec7bfb77d /tests/memlib/memlib_wide_read.v | |
| parent | 2a2dc12eb69f2e904609e5b8275ec885e21ecd26 (diff) | |
| download | yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.tar.gz yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.tar.bz2 yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.zip | |
Add memory_libmap tests.
Diffstat (limited to 'tests/memlib/memlib_wide_read.v')
| -rw-r--r-- | tests/memlib/memlib_wide_read.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/memlib/memlib_wide_read.v b/tests/memlib/memlib_wide_read.v new file mode 100644 index 000000000..e45f64376 --- /dev/null +++ b/tests/memlib/memlib_wide_read.v @@ -0,0 +1,25 @@ +module RAM_WIDE_READ #( + parameter [63:0] INIT = 64'hx, + parameter PORT_A_RD_WIDTH = 8, + parameter PORT_A_WR_WIDTH = 2 +) ( + input PORT_A_CLK, + input PORT_A_RD_EN, + input [5:0] PORT_A_ADDR, + output reg [7:0] PORT_A_RD_DATA, + input PORT_A_WR_EN, + input [1:0] PORT_A_WR_DATA +); + +reg [63:0] mem; + +initial mem = INIT; + +always @(posedge PORT_A_CLK) begin + if (PORT_A_RD_EN) + PORT_A_RD_DATA <= mem[{PORT_A_ADDR[5:3], 3'b000}+:8]; + if (PORT_A_WR_EN) + mem[{PORT_A_ADDR[5:1],1'b0}+:2] <= PORT_A_WR_DATA; +end + +endmodule |