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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-05-29 17:45:05 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-14 00:09:04 +0200 |
commit | 1f74ec3535dba67d3e71ab1b9bf509c86bdca560 (patch) | |
tree | b8c2bc221e0fe7161095fe7332520414a5d0fb6b /tests/memories/wide_thru_priority.v | |
parent | 9fdedf4d1c5b1715f98ad107d322966eaee91f20 (diff) | |
download | yosys-1f74ec3535dba67d3e71ab1b9bf509c86bdca560.tar.gz yosys-1f74ec3535dba67d3e71ab1b9bf509c86bdca560.tar.bz2 yosys-1f74ec3535dba67d3e71ab1b9bf509c86bdca560.zip |
memory_share: Add -nosat and -nowiden options.
This unlocks wide port recognition by default.
Diffstat (limited to 'tests/memories/wide_thru_priority.v')
-rw-r--r-- | tests/memories/wide_thru_priority.v | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/tests/memories/wide_thru_priority.v b/tests/memories/wide_thru_priority.v new file mode 100644 index 000000000..10c0d837b --- /dev/null +++ b/tests/memories/wide_thru_priority.v @@ -0,0 +1,29 @@ +// expect-wr-ports 3 +// expect-rd-ports 1 +// expect-wr-wide-continuation 3'010 + +module test( + input clk, + input we1, we2, + input [5:0] ra, + input [4:0] wa1, + input [5:0] wa2, + input [15:0] wd1, + input [7:0] wd2, + output [7:0] rd +); + +reg [7:0] mem[0:63]; + +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) + mem[{wa1, 1'b0}] <= wd1[7:0]; + if (we2) + mem[wa2] <= wd2; + if (we1) + mem[{wa1, 1'b1}] <= wd1[15:8]; +end + +endmodule |