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author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-01 13:16:01 -0700 |
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committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-01 13:16:01 -0700 |
commit | 38f5424f92389d6f4fdf020b214023b2b6efa71a (patch) | |
tree | 0c3bb206b6ec82177eba5794e37d9b422af1a351 /tests/memories | |
parent | e35fe1344dd4c8f11632ed2a7f5b0463352a1ee4 (diff) | |
download | yosys-38f5424f92389d6f4fdf020b214023b2b6efa71a.tar.gz yosys-38f5424f92389d6f4fdf020b214023b2b6efa71a.tar.bz2 yosys-38f5424f92389d6f4fdf020b214023b2b6efa71a.zip |
Fix #938 - Crash occurs in case when use write_firrtl command
Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
Diffstat (limited to 'tests/memories')
-rw-r--r-- | tests/memories/firrtl_938.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/memories/firrtl_938.v b/tests/memories/firrtl_938.v new file mode 100644 index 000000000..af5efcd25 --- /dev/null +++ b/tests/memories/firrtl_938.v @@ -0,0 +1,22 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end + +endmodule |