diff options
author | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 08:43:58 -0700 |
---|---|---|
committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 08:43:58 -0700 |
commit | ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7 (patch) | |
tree | 2f3ede3fb804ed9268ca759075551a09caf4fe96 /tests/memories | |
parent | add2d415fcab64eae8819021ad1b8dd1b56e6bf2 (diff) | |
download | yosys-ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7.tar.gz yosys-ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7.tar.bz2 yosys-ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7.zip |
Add testcase from #335, fixed by #1130
Diffstat (limited to 'tests/memories')
-rw-r--r-- | tests/memories/issue00335.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v new file mode 100644 index 000000000..f3b6e5dfe --- /dev/null +++ b/tests/memories/issue00335.v @@ -0,0 +1,28 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk + +module ram2 (input clk, + input sel, + input we, + input [SIZE-1:0] adr, + input [63:0] dat_i, + output reg [63:0] dat_o); + parameter SIZE = 5; // Address size + + reg [63:0] mem [0:(1 << SIZE)-1]; + integer i; + + initial begin + for (i = 0; i < (1<<SIZE) - 1; i = i + 1) + mem[i] <= 0; + end + + always @(posedge clk) + if (sel) begin + if (~we) + dat_o <= mem[adr]; + else + mem[adr] <= dat_i; + end +endmodule |