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| author | David Shah <davey1576@gmail.com> | 2019-08-10 17:14:48 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-10 17:14:48 +0100 |
| commit | f9020ce2b35f2fc205fc71cb095efce1a24fd86d (patch) | |
| tree | 73ac462dd723cc389070cea893ddc9c1998339a2 /tests/opt/opt_expr.ys | |
| parent | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (diff) | |
| download | yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.gz yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.bz2 yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.zip | |
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
Diffstat (limited to 'tests/opt/opt_expr.ys')
| -rw-r--r-- | tests/opt/opt_expr.ys | 148 |
1 files changed, 0 insertions, 148 deletions
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys deleted file mode 100644 index 0c61ac881..000000000 --- a/tests/opt/opt_expr.ys +++ /dev/null @@ -1,148 +0,0 @@ - -read_verilog <<EOT -module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) + j; -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -opt_expr -fine -wreduce - -select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -########## - -read_verilog <<EOT -module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); - assign o = (i << 4) + j; -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -opt_expr -fine -wreduce - -select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -########## - -read_verilog <<EOT -module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = j - (i << 4); -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -opt_expr -fine -wreduce - -select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -########## - -read_verilog <<EOT -module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); - assign o = j - (i << 4); -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -opt_expr -fine -wreduce - -select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -########## - -read_verilog <<EOT -module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) - j; -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -opt_expr -fine -wreduce - -select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -########## - -read_verilog <<EOT -module opt_expr_sub_test4(input [3:0] i, output [8:0] o); - assign o = 5'b00010 - i; -endmodule -EOT - -hierarchy -auto-top -proc -design -save gold - -opt_expr -fine -wreduce - -select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter |