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| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-24 11:45:38 +0200 |
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| committer | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-24 11:56:26 +0200 |
| commit | a5ca4eeefb13c24042bae36ea8f640b5529efd93 (patch) | |
| tree | a35f4ef3b18f2baa6cd5fa8d88c8719d0d597378 /tests/opt/opt_expr_or_assignment.ys | |
| parent | 22408f24c7d9c8a648e854fad01aff37a0f9fbd9 (diff) | |
| download | yosys-a5ca4eeefb13c24042bae36ea8f640b5529efd93.tar.gz yosys-a5ca4eeefb13c24042bae36ea8f640b5529efd93.tar.bz2 yosys-a5ca4eeefb13c24042bae36ea8f640b5529efd93.zip | |
Add or-assignment and plus-assignment tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Diffstat (limited to 'tests/opt/opt_expr_or_assignment.ys')
| -rw-r--r-- | tests/opt/opt_expr_or_assignment.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/opt/opt_expr_or_assignment.ys b/tests/opt/opt_expr_or_assignment.ys new file mode 100644 index 000000000..21e08550f --- /dev/null +++ b/tests/opt/opt_expr_or_assignment.ys @@ -0,0 +1,15 @@ +read_verilog -sv <<EOT +module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b0; +initial begin + a |= i; + a |= j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i |