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author | David Shah <davey1576@gmail.com> | 2019-08-10 17:14:48 +0100 |
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committer | GitHub <noreply@github.com> | 2019-08-10 17:14:48 +0100 |
commit | f9020ce2b35f2fc205fc71cb095efce1a24fd86d (patch) | |
tree | 73ac462dd723cc389070cea893ddc9c1998339a2 /tests/opt/opt_ff.v | |
parent | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (diff) | |
download | yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.gz yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.bz2 yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.zip |
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
Diffstat (limited to 'tests/opt/opt_ff.v')
-rw-r--r-- | tests/opt/opt_ff.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/opt/opt_ff.v b/tests/opt/opt_ff.v new file mode 100644 index 000000000..a01b64b61 --- /dev/null +++ b/tests/opt/opt_ff.v @@ -0,0 +1,21 @@ +module top( + input clk, + input rst, + input [2:0] a, + output [1:0] b +); + reg [2:0] b_reg; + initial begin + b_reg <= 3'b0; + end + + assign b = b_reg[1:0]; + always @(posedge clk or posedge rst) begin + if(rst) begin + b_reg <= 3'b0; + end else begin + b_reg <= a; + end + end +endmodule + |