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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-05 09:02:13 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-05 09:02:13 -0800 |
| commit | 50a94ce4fc64ef4b95dba4119e82df01680b0617 (patch) | |
| tree | c5dff0100358efc89b90995603b9b4365777e4bb /tests/opt/opt_lut.ys | |
| parent | 11323665aff4c4af612f12fb3dda5096ace26a7d (diff) | |
| parent | 45cb6200af13469724de42656f2c1f0f61c8766a (diff) | |
| download | yosys-50a94ce4fc64ef4b95dba4119e82df01680b0617.tar.gz yosys-50a94ce4fc64ef4b95dba4119e82df01680b0617.tar.bz2 yosys-50a94ce4fc64ef4b95dba4119e82df01680b0617.zip | |
Merge pull request #717 from whitequark/opt_lut
Add a new opt_lut pass, which combines inefficiently packed LUTs
Diffstat (limited to 'tests/opt/opt_lut.ys')
| -rw-r--r-- | tests/opt/opt_lut.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys new file mode 100644 index 000000000..86ad93bb3 --- /dev/null +++ b/tests/opt/opt_lut.ys @@ -0,0 +1,15 @@ +read_verilog opt_lut.v +synth_ice40 +ice40_unlut +design -save preopt + +opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 +design -stash postopt + +design -copy-from preopt -as preopt top +design -copy-from postopt -as postopt top +equiv_make preopt postopt equiv +techmap -map ice40_carry.v +prep -flatten -top equiv +equiv_induct +equiv_status -assert |