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| author | David Shah <davey1576@gmail.com> | 2019-08-10 17:14:48 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-10 17:14:48 +0100 |
| commit | f9020ce2b35f2fc205fc71cb095efce1a24fd86d (patch) | |
| tree | 73ac462dd723cc389070cea893ddc9c1998339a2 /tests/opt/opt_lut.ys | |
| parent | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (diff) | |
| download | yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.gz yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.bz2 yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.zip | |
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
Diffstat (limited to 'tests/opt/opt_lut.ys')
| -rw-r--r-- | tests/opt/opt_lut.ys | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys index a9fccbb62..59b12c351 100644 --- a/tests/opt/opt_lut.ys +++ b/tests/opt/opt_lut.ys @@ -1,2 +1,4 @@ read_verilog opt_lut.v -equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40 +synth_ice40 +ice40_unlut +equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 |