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| author | Rodrigo A. Melo <rmelo@inti.gob.ar> | 2020-02-03 11:07:51 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-03 11:07:51 -0300 |
| commit | 665a967d879d4ed5af8d3518e6cd02afae244f97 (patch) | |
| tree | 666525ed070696a2274e505b662d63def645a0d3 /tests/opt | |
| parent | 313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc (diff) | |
| parent | 34d2fbd2f96a8789aa7eb655318308e11949eb7a (diff) | |
| download | yosys-665a967d879d4ed5af8d3518e6cd02afae244f97.tar.gz yosys-665a967d879d4ed5af8d3518e6cd02afae244f97.tar.bz2 yosys-665a967d879d4ed5af8d3518e6cd02afae244f97.zip | |
Merge branch 'master' into master
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/opt_lut_ins.ys | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/opt/opt_lut_ins.ys b/tests/opt/opt_lut_ins.ys new file mode 100644 index 000000000..82460b164 --- /dev/null +++ b/tests/opt/opt_lut_ins.ys @@ -0,0 +1,23 @@ +read_ilang << EOF + +module \top + + wire width 4 input 1 \A + + wire output 2 \Y + + cell $lut \lut + parameter \LUT 16'1111110011000000 + parameter \WIDTH 4 + connect \A \A + connect \Y \Y + end +end + +EOF + +equiv_opt -assert opt_lut_ins + +design -load postopt + +select -assert-count 1 t:$lut r:WIDTH=3 %i |