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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-10-08 13:33:47 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-10-08 18:05:51 +0200 |
commit | 7670a89e1fde7d0774695ab81031a90fafdf56b9 (patch) | |
tree | 063e90c411b1e76e395460c27402a9a504b7f00d /tests/opt | |
parent | fd306b0520ac42323cbfacfa3a41e7a7a9379ec0 (diff) | |
download | yosys-7670a89e1fde7d0774695ab81031a90fafdf56b9.tar.gz yosys-7670a89e1fde7d0774695ab81031a90fafdf56b9.tar.bz2 yosys-7670a89e1fde7d0774695ab81031a90fafdf56b9.zip |
opt_clean: Better memory handling.
Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself). With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
Diffstat (limited to 'tests/opt')
-rw-r--r-- | tests/opt/opt_clean_mem.ys | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/tests/opt/opt_clean_mem.ys b/tests/opt/opt_clean_mem.ys new file mode 100644 index 000000000..b35b15871 --- /dev/null +++ b/tests/opt/opt_clean_mem.ys @@ -0,0 +1,49 @@ +read_verilog <<EOT +module top(...); + +input [7:0] wa; +input [7:0] ra1; +input [7:0] ra2; +input [7:0] wd; +input clk; +wire [7:0] rd1; +wire [7:0] rd2; + +reg [7:0] mem[0:7]; + +always @(posedge clk) + mem[wa] <= wd; +assign rd1 = mem[ra1]; +assign rd2 = mem[ra2]; + +initial mem[8'h12] = 8'h34; + +endmodule +EOT + +proc +memory_dff + +select -assert-count 2 t:$memrd +select -assert-count 1 t:$memwr +select -assert-count 1 t:$meminit +design -save orig + +opt_clean +select -assert-none t:$memrd +select -assert-none t:$memwr +select -assert-none t:$meminit + +design -load orig +expose top/rd1 +opt_clean +select -assert-count 1 t:$memrd +select -assert-count 1 t:$memwr +select -assert-count 1 t:$meminit + +design -load orig +expose top/rd1 top/rd2 +opt_clean +select -assert-count 2 t:$memrd +select -assert-count 1 t:$memwr +select -assert-count 1 t:$meminit |