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| author | whitequark <whitequark@whitequark.org> | 2019-08-20 00:45:41 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-20 00:45:41 +0000 |
| commit | 749ff864aa708cb069fc5c356e5db69664fdd93e (patch) | |
| tree | e120c95f7f307d10e146067b064774eddf146587 /tests/proc/bug_1268.ys | |
| parent | 3f4886e7a3ff14578b9c6d614efd360478e5886e (diff) | |
| parent | 4a942ba7b9bb76f207adf23369f46d31f7607b75 (diff) | |
| download | yosys-749ff864aa708cb069fc5c356e5db69664fdd93e.tar.gz yosys-749ff864aa708cb069fc5c356e5db69664fdd93e.tar.bz2 yosys-749ff864aa708cb069fc5c356e5db69664fdd93e.zip | |
Merge pull request #1309 from whitequark/proc_clean-fix-1268
proc_clean: fix order of switch insertion
Diffstat (limited to 'tests/proc/bug_1268.ys')
| -rw-r--r-- | tests/proc/bug_1268.ys | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/proc/bug_1268.ys b/tests/proc/bug_1268.ys new file mode 100644 index 000000000..b73e94449 --- /dev/null +++ b/tests/proc/bug_1268.ys @@ -0,0 +1,5 @@ +read_verilog bug_1268.v +proc +equiv_make gold gate equiv +equiv_induct +equiv_status -assert |