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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:42:19 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:43:08 -0700 |
commit | 51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d (patch) | |
tree | 2a70d1550ab81a96f4c383524fd4c66bdef2c7b0 /tests/sat/initval.ys | |
parent | c50d68653d093a8daa47f589836e6178be82b54f (diff) | |
download | yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.tar.gz yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.tar.bz2 yosys-51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d.zip |
In sat: 'x' in init attr should not override constant
Diffstat (limited to 'tests/sat/initval.ys')
-rw-r--r-- | tests/sat/initval.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..3d88aa971 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc;; +proc; sat -seq 10 -prove-asserts |