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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-02-21 17:57:44 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-21 17:57:44 +0100 |
| commit | d0b72e75d95828743b38184ee977c3c56f259b38 (patch) | |
| tree | d4cdb702831ad471a26c4f96f70900f701166a05 /tests/sim/dlatchsr.v | |
| parent | d0f4d0b153572ddee5f19831f40b9c40eb480db0 (diff) | |
| parent | fd3f08753a2c577bb87ad332329213c58d4a9326 (diff) | |
| download | yosys-d0b72e75d95828743b38184ee977c3c56f259b38.tar.gz yosys-d0b72e75d95828743b38184ee977c3c56f259b38.tar.bz2 yosys-d0b72e75d95828743b38184ee977c3c56f259b38.zip | |
Merge pull request #3203 from YosysHQ/micko/sim_ff
Simulation for various FF types
Diffstat (limited to 'tests/sim/dlatchsr.v')
| -rw-r--r-- | tests/sim/dlatchsr.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/sim/dlatchsr.v b/tests/sim/dlatchsr.v new file mode 100644 index 000000000..1d13ac2ad --- /dev/null +++ b/tests/sim/dlatchsr.v @@ -0,0 +1,11 @@ +module dlatchsr( input d, set, clr, en, output reg q ); + always @* begin + if ( clr ) + q = 0; + else if (set) + q = 1; + else + if (en) + q = d; + end +endmodule |