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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-15 09:35:53 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-16 13:27:59 +0100 |
| commit | 271ac28b417be00d7be1cc898762c8e425a0aae3 (patch) | |
| tree | fcff14974c070b2615e8eda981e5b811fc4e8905 /tests/sim/run-test.sh | |
| parent | fb22d7cdc411ec52672cb7f13364651c564872db (diff) | |
| download | yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.tar.gz yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.tar.bz2 yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.zip | |
Added test cases
Diffstat (limited to 'tests/sim/run-test.sh')
| -rwxr-xr-x | tests/sim/run-test.sh | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/sim/run-test.sh b/tests/sim/run-test.sh new file mode 100755 index 000000000..d34d1f3c9 --- /dev/null +++ b/tests/sim/run-test.sh @@ -0,0 +1,12 @@ +#!/usr/bin/env bash +set -eu +source ../gen-tests-makefile.sh +echo "Generate FST for sim models" +find tb/* -name tb*.v | while read name; do + test_name=$(basename -s .v $name) + echo "Test $test_name" + verilog_name=${test_name:3}.v + iverilog -o tb/$test_name.out $name $verilog_name + ./tb/$test_name.out -fst +done +run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" |