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author | Claire Xenia Wolf <claire@clairexen.net> | 2021-09-22 17:34:20 +0200 |
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committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-09-23 14:54:28 +0200 |
commit | 15fb0107dcdfcf98c56f229727c7cd701ff9b4b3 (patch) | |
tree | 53d8c5a6530545103701e0842d926b40a657748c /tests/simple/attrib02_port_decl.v | |
parent | 3931b3a03f65965daca20b1228d8882192e74650 (diff) | |
download | yosys-15fb0107dcdfcf98c56f229727c7cd701ff9b4b3.tar.gz yosys-15fb0107dcdfcf98c56f229727c7cd701ff9b4b3.tar.bz2 yosys-15fb0107dcdfcf98c56f229727c7cd701ff9b4b3.zip |
Fix "make vgtest" so it runs to the end (but now it fails ;)
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'tests/simple/attrib02_port_decl.v')
-rw-r--r-- | tests/simple/attrib02_port_decl.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v index 3505e7265..989213b77 100644 --- a/tests/simple/attrib02_port_decl.v +++ b/tests/simple/attrib02_port_decl.v @@ -1,4 +1,4 @@ -module bar(clk, rst, inp, out); +module attrib02_bar(clk, rst, inp, out); (* this_is_clock = 1 *) input wire clk; (* this_is_reset = 1 *) @@ -13,13 +13,13 @@ module bar(clk, rst, inp, out); endmodule -module foo(clk, rst, inp, out); +module attrib02_foo(clk, rst, inp, out); (* this_is_the_master_clock *) input wire clk; input wire rst; input wire inp; output wire out; - bar bar_instance (clk, rst, inp, out); + attrib02_bar bar_instance (clk, rst, inp, out); endmodule |