Merge pull request #2529 from zachjs/unnamed-genblk

verilog: significant block scoping improvements

1 files changed, 33 insertions, 0 deletions

diff --git a/tests/simple/func_block.v b/tests/simple/func_block.v
new file mode 100644
index 000000000..be759d1a9
--- /dev/null
+++ b/tests/simple/func_block.v
@@ -0,0 +1,33 @@
+`default_nettype none
+
+module top(inp, out1, out2, out3);
+	input wire [31:0] inp;
+
+	function automatic [31:0] func1;
+		input [31:0] inp;
+		reg [31:0] idx;
+		for (idx = 0; idx < 32; idx = idx + 1) begin : blk
+			func1[idx] = (idx & 1'b1) ^ inp[idx];
+		end
+	endfunction
+
+	function automatic [31:0] func2;
+		input [31:0] inp;
+		reg [31:0] idx;
+		for (idx = 0; idx < 32; idx = idx + 1) begin : blk
+			func2[idx] = (idx & 1'b1) ^ inp[idx];
+		end
+	endfunction
+
+	function automatic [31:0] func3;
+		localparam A = 32 - 1;
+		parameter B = 1 - 0;
+		input [31:0] inp;
+		func3[A:B] = inp[A:B];
+	endfunction
+
+	output wire [31:0] out1, out2, out3;
+	assign out1 = func1(inp);
+	assign out2 = func2(inp);
+	assign out3 = func3(inp);
+endmodule