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author | whitequark <whitequark@whitequark.org> | 2021-02-04 09:57:28 +0000 |
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committer | GitHub <noreply@github.com> | 2021-02-04 09:57:28 +0000 |
commit | baf1875307f1608762169d3037ba005da88b201e (patch) | |
tree | 44b84ab2ef42251cdc916a417e105c3f172c2a19 /tests/simple/func_recurse.v | |
parent | afcc31ceba35d33fc11f9e1592956bb4112ca0e3 (diff) | |
parent | fe74b0cd95267bc78953236311382653a6db7f60 (diff) | |
download | yosys-baf1875307f1608762169d3037ba005da88b201e.tar.gz yosys-baf1875307f1608762169d3037ba005da88b201e.tar.bz2 yosys-baf1875307f1608762169d3037ba005da88b201e.zip |
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
Diffstat (limited to 'tests/simple/func_recurse.v')
-rw-r--r-- | tests/simple/func_recurse.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/simple/func_recurse.v b/tests/simple/func_recurse.v new file mode 100644 index 000000000..d61c8cc06 --- /dev/null +++ b/tests/simple/func_recurse.v @@ -0,0 +1,25 @@ +module top( + input wire [3:0] inp, + output wire [3:0] out1, out2 +); + function automatic [3:0] pow_a; + input [3:0] base, exp; + begin + pow_a = 1; + if (exp > 0) + pow_a = base * pow_a(base, exp - 1); + end + endfunction + + function automatic [3:0] pow_b; + input [3:0] base, exp; + begin + pow_b = 1; + if (exp > 0) + pow_b = base * pow_b(base, exp - 1); + end + endfunction + + assign out1 = pow_a(inp, 3); + assign out2 = pow_b(2, 2); +endmodule |