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| author | whitequark <whitequark@whitequark.org> | 2021-02-04 09:57:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-04 09:57:28 +0000 |
| commit | baf1875307f1608762169d3037ba005da88b201e (patch) | |
| tree | 44b84ab2ef42251cdc916a417e105c3f172c2a19 /tests/simple/genblk_order.v | |
| parent | afcc31ceba35d33fc11f9e1592956bb4112ca0e3 (diff) | |
| parent | fe74b0cd95267bc78953236311382653a6db7f60 (diff) | |
| download | yosys-baf1875307f1608762169d3037ba005da88b201e.tar.gz yosys-baf1875307f1608762169d3037ba005da88b201e.tar.bz2 yosys-baf1875307f1608762169d3037ba005da88b201e.zip | |
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
Diffstat (limited to 'tests/simple/genblk_order.v')
| -rw-r--r-- | tests/simple/genblk_order.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/simple/genblk_order.v b/tests/simple/genblk_order.v new file mode 100644 index 000000000..7c3a7a756 --- /dev/null +++ b/tests/simple/genblk_order.v @@ -0,0 +1,18 @@ +`default_nettype none +module top( + output wire out1, + output wire out2 +); + generate + if (1) begin : outer + if (1) begin : foo + wire x = 0; + if (1) begin : foo + wire x = 1; + assign out1 = foo.x; + end + assign out2 = foo.x; + end + end + endgenerate +endmodule |