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| author | Zachary Snow <zach@zachjs.com> | 2021-02-25 15:53:55 -0500 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-03-01 12:28:33 -0500 |
| commit | 1ec5994100510d6fb9e18ff7234ede496f831a51 (patch) | |
| tree | 77c8403f0ece00ad1b42e2e91f86befe0f736cac /tests/simple/ifdef_1.v | |
| parent | b6904a8e5344fcd01c1a0feea281cd7d7bf0f210 (diff) | |
| download | yosys-1ec5994100510d6fb9e18ff7234ede496f831a51.tar.gz yosys-1ec5994100510d6fb9e18ff7234ede496f831a51.tar.bz2 yosys-1ec5994100510d6fb9e18ff7234ede496f831a51.zip | |
verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
Diffstat (limited to 'tests/simple/ifdef_1.v')
| -rw-r--r-- | tests/simple/ifdef_1.v | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/tests/simple/ifdef_1.v b/tests/simple/ifdef_1.v new file mode 100644 index 000000000..fa962355c --- /dev/null +++ b/tests/simple/ifdef_1.v @@ -0,0 +1,88 @@ +module top(o1, o2, o3, o4); + +`define FAIL input wire not_a_port; + +`ifdef COND_1 + `FAIL +`elsif COND_2 + `FAIL +`elsif COND_3 + `FAIL +`elsif COND_4 + `FAIL +`else + + `define COND_4 + output wire o4; + + `ifdef COND_1 + `FAIL + `elsif COND_2 + `FAIL + `elsif COND_3 + `FAIL + `elsif COND_4 + + `define COND_3 + output wire o3; + + `ifdef COND_1 + `FAIL + `elsif COND_2 + `FAIL + `elsif COND_3 + + `define COND_2 + output wire o2; + + `ifdef COND_1 + `FAIL + `elsif COND_2 + + `define COND_1 + output wire o1; + + `ifdef COND_1 + + `ifdef COND_1 + `elsif COND_2 + `FAIL + `elsif COND_3 + `FAIL + `elsif COND_4 + `FAIL + `else + `FAIL + `endif + + `elsif COND_2 + `FAIL + `elsif COND_3 + `FAIL + `elsif COND_4 + `FAIL + `else + `FAIL + `endif + + `elsif COND_3 + `FAIL + `elsif COND_4 + `FAIL + `else + `FAIL + `endif + + `elsif COND_4 + `FAIL + `else + `FAIL + `endif + + `else + `FAIL + `endif + +`endif + +endmodule |