diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
| commit | c06c062469a6f5ea16116a5ed3bc4a45b6e818a2 (patch) | |
| tree | ea54f3510f2e85771422718385028b0864696cba /tests/simple/xfirrtl | |
| parent | 8ddec5d882c6834cb6b3415e05a2a88d416cabff (diff) | |
| parent | e45f62b0c56717a23099425f078d1e56212aa632 (diff) | |
| download | yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.gz yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.bz2 yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
Diffstat (limited to 'tests/simple/xfirrtl')
| -rw-r--r-- | tests/simple/xfirrtl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl new file mode 100644 index 000000000..00e89b389 --- /dev/null +++ b/tests/simple/xfirrtl @@ -0,0 +1,26 @@ +# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures. +arraycells.v inst id[0] of +dff_different_styles.v +generate.v combinational loop +hierdefparam.v inst id[0] of +i2c_master_tests.v $adff +macros.v drops modules +mem2reg.v drops modules +mem_arst.v $adff +memory.v $adff +multiplier.v inst id[0] of +muxtree.v drops modules +omsp_dbg_uart.v $adff +operators.v $pow +paramods.v subfield assignment (bits() <= ...) +partsel.v drops modules +process.v drops modules +realexpr.v drops modules +scopes.v original verilog issues ( -x where x isn't declared signed) +sincos.v $adff +specify.v no code (empty module generates error +subbytes.v $adff +task_func.v drops modules +values.v combinational loop +vloghammer.v combinational loop +wreduce.v original verilog issues ( -x where x isn't declared signed) |