Another block of spelling fixes

Smaller this time

4 files changed, 6 insertions, 6 deletions

diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v
index 2f2737c4c..7765d6e2a 100644
--- a/tests/simple/dff_different_styles.v
+++ b/tests/simple/dff_different_styles.v
@@ -65,7 +65,7 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
 end
 endmodule
 
-// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of
+// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of
 // simulation-implementation mismatches. The following testcases try to cover the
 // part that is defined and avoid the undefined cases.
 
diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v
index 17888009f..123afaeab 100644
--- a/tests/simple/hierarchy.v
+++ b/tests/simple/hierarchy.v
@@ -5,10 +5,10 @@ input [3:0] a;
 input signed [3:0] b;
 output [7:0] y1, y2, y3, y4;
 
-// this version triggers a bug in icarus verilog
+// this version triggers a bug in Icarus Verilog
 // submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
 
-// this version is handled correctly by icarus verilog
+// this version is handled correctly by Icarus Verilog
 submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
 
 endmodule
diff --git a/tests/simple/rotate.v b/tests/simple/rotate.v
index eb832e6f5..a2fe00055 100644
--- a/tests/simple/rotate.v
+++ b/tests/simple/rotate.v
@@ -1,5 +1,5 @@
 
-// test case taken from amber23 verilog code
+// test case taken from amber23 Verilog code
 module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
 
 input  [31:0] i_in;
diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index d1f55fdb4..3bb3cf992 100644
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -27,14 +27,14 @@ module test04(a, y);
   assign y = ~(a - 1'b0);
 endmodule
 
-// .. this test triggers a bug in xilinx isim.
+// .. this test triggers a bug in Xilinx ISIM.
 // module test05(a, y);
 //   input a;
 //   output y;
 //   assign y = 12345 >> {a, 32'd0};
 // endmodule
 
-// .. this test triggers a bug in icarus verilog.
+// .. this test triggers a bug in Icarus Verilog.
 // module test06(a, b, c, y);
 //   input signed [3:0] a;
 //   input signed [1:0] b;