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author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 11:26:20 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 11:26:20 +0100 |
commit | 913c304fe62cb962e32fa0eb024fa4fc3110639c (patch) | |
tree | d8f2026012c619c229132bbdc19e4e22017a2c0f /tests/simple | |
parent | 7f1a1759d7cdbbb528c451bf8fc8baf3b7e72893 (diff) | |
download | yosys-913c304fe62cb962e32fa0eb024fa4fc3110639c.tar.gz yosys-913c304fe62cb962e32fa0eb024fa4fc3110639c.tar.bz2 yosys-913c304fe62cb962e32fa0eb024fa4fc3110639c.zip |
Added $meminit test case
Diffstat (limited to 'tests/simple')
-rw-r--r-- | tests/simple/memory.v | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v index db06c56d2..f7c37309c 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -205,3 +205,33 @@ module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y); end endmodule +// ---------------------------------------------------------- + +module memtest09 ( + input clk, + input [1:0] a_addr, a_din, b_addr, b_din, + input a_wen, b_wen, + output reg [1:0] a_dout, b_dout +); + reg [1:0] memory [0:3]; + + initial begin + memory[0] <= 0; + memory[1] <= 1; + memory[2] <= 2; + memory[3] <= 3; + end + + always @(posedge clk) begin + if (a_wen) + memory[a_addr] <= a_din; + a_dout <= memory[a_addr]; + end + + always @(posedge clk) begin + if (b_wen) + memory[b_addr] <= b_din; + b_dout <= memory[b_addr]; + end +endmodule + |