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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-08 14:31:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-08 14:31:06 +0200 |
| commit | 9a101dc1f78acb404cc98e0acc4530c238070fd8 (patch) | |
| tree | d64e52953a422d8c7d0c8b3d5841bdd2a1dea966 /tests/simple | |
| parent | b782076698b76445b6b1087671687483c6d6c545 (diff) | |
| download | yosys-9a101dc1f78acb404cc98e0acc4530c238070fd8.tar.gz yosys-9a101dc1f78acb404cc98e0acc4530c238070fd8.tar.bz2 yosys-9a101dc1f78acb404cc98e0acc4530c238070fd8.zip | |
Fixed mem assignment in left-hand-side concatenation
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/memory.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v index 9fddce26c..61b36e79a 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -264,3 +264,16 @@ module memtest11(clk, wen, waddr, raddr, wdata, rdata); end endmodule +// ---------------------------------------------------------- + +module memtest12 ( + input clk, + input [1:0] adr, + input [1:0] din, + output reg [1:0] q +); + reg [1:0] ram [3:0]; + always@(posedge clk) + {ram[adr], q} <= {din, ram[adr]}; +endmodule + |