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author | Zachary Snow <zach@zachjs.com> | 2021-05-26 18:22:31 -0400 |
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committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-06-08 15:02:57 -0400 |
commit | c79fbfe0a130f1a2979413174c3e5688433bafe3 (patch) | |
tree | 4779bf4befa1f9459d96566a3ff70af287bb5aa4 /tests/simple | |
parent | d9f11bb7a631ad309b9328d33b2f41a4987b6222 (diff) | |
download | yosys-c79fbfe0a130f1a2979413174c3e5688433bafe3.tar.gz yosys-c79fbfe0a130f1a2979413174c3e5688433bafe3.tar.bz2 yosys-c79fbfe0a130f1a2979413174c3e5688433bafe3.zip |
mem2reg: tolerate out of bounds constant accesses
This brings the mem2reg behavior in line with the nomem2reg behavior.
Diffstat (limited to 'tests/simple')
-rw-r--r-- | tests/simple/mem2reg_bounds_tern.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/simple/mem2reg_bounds_tern.v b/tests/simple/mem2reg_bounds_tern.v new file mode 100644 index 000000000..89d6dd3e8 --- /dev/null +++ b/tests/simple/mem2reg_bounds_tern.v @@ -0,0 +1,19 @@ +module top( + input clk, + input wire [1:0] sel, + input wire [7:0] base, + output reg [7:0] line +); + reg [0:7] mem [0:2]; + + generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin : gen + always @(posedge clk) + mem[i] <= i == 0 ? base : mem[i - 1] + 1; + end + endgenerate + + always @(posedge clk) + line = mem[sel]; +endmodule |