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| author | Claire Xen <claire@clairexen.net> | 2021-03-01 18:00:48 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-01 18:00:48 +0100 |
| commit | 004b780b8abf4e8fdf88831cd3e77767d660f108 (patch) | |
| tree | db7675b5444b069eed1aebbcc4b41ba743f2c894 /tests/simple_abc9 | |
| parent | 527c681a2b2c567e73be242cacdf163c3bf7a2ac (diff) | |
| parent | 3a8eecebbad01f2a73ddf4efd0949b9ba5684506 (diff) | |
| download | yosys-004b780b8abf4e8fdf88831cd3e77767d660f108.tar.gz yosys-004b780b8abf4e8fdf88831cd3e77767d660f108.tar.bz2 yosys-004b780b8abf4e8fdf88831cd3e77767d660f108.zip | |
Merge pull request #2523 from tomverbeure/define_synthesis
Add -nosynthesis flag for read_verilog command
Diffstat (limited to 'tests/simple_abc9')
0 files changed, 0 insertions, 0 deletions