diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2021-03-29 22:01:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-29 22:01:57 -0700 |
| commit | 55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8 (patch) | |
| tree | ab4ab932ea29088baafcf3c71d6c5854403528d6 /tests/simple_abc9 | |
| parent | 687f381b6985d9dda7e11535628e2fafff267af5 (diff) | |
| download | yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.tar.gz yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.tar.bz2 yosys-55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8.zip | |
abc9: fix SCC issues (#2694)
* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
Diffstat (limited to 'tests/simple_abc9')
| -rw-r--r-- | tests/simple_abc9/abc9.box | 3 | ||||
| -rw-r--r-- | tests/simple_abc9/abc9.v | 24 | ||||
| -rwxr-xr-x | tests/simple_abc9/run-test.sh | 12 |
3 files changed, 27 insertions, 12 deletions
diff --git a/tests/simple_abc9/abc9.box b/tests/simple_abc9/abc9.box deleted file mode 100644 index b3c88437c..000000000 --- a/tests/simple_abc9/abc9.box +++ /dev/null @@ -1,3 +0,0 @@ -MUXF8 1 0 3 1 -#I0 I1 S -0 0 0 # O diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 5e969c614..fba089b1f 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box_id=1, blackbox *) +(* abc9_box, blackbox *) module MUXF8(input I0, I1, S, output O); specify (I0 => O) = 0; @@ -300,15 +300,29 @@ endmodule module abc9_test036(input A, B, S, output [1:0] O); (* keep *) MUXF8 m ( - .I0(I0), - .I1(I1), + .I0(A), + .I1(B), .O(O[0]), .S(S) ); MUXF8 m2 ( - .I0(I0), - .I1(I1), + .I0(A), + .I1(B), .O(O[1]), .S(S) ); endmodule + +(* abc9_box, whitebox *) +module MUXF7(input I0, I1, S, output O); +assign O = S ? I1 : I0; +specify + (I0 => O) = 0; + (I1 => O) = 0; + (S => O) = 0; +endspecify +endmodule + +module abc9_test037(output o); +MUXF7 m(.I0(1'b1), .I1(1'b0), .S(o), .O(o)); +endmodule diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index b48505e29..4a5bf01a3 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -37,14 +37,18 @@ done cp ../simple/*.v . cp ../simple/*.sv . +rm specify.v # bug 2675 DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p '\ +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-f \"verilog -noblackbox -specify\" -n 300 -p '\ + read_verilog -icells -lib +/abc9_model.v; \ hierarchy; \ synth -run coarse; \ opt -full; \ techmap; \ - abc9 -lut 4 -box ../abc9.box; \ + abc9 -lut 4; \ clean; \ - check -assert; \ + check -assert * abc9_test037 %d; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ - setattr -mod -unset blackbox'" + setattr -mod -unset blackbox -unset whitebox'" + +# NOTE: Skip 'check -assert' on abc9_test037 because it intentionally has a combinatorial loop |