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| author | clairexen <claire@symbioticeda.com> | 2020-07-02 17:46:11 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-02 17:46:11 +0200 |
| commit | 5428666151be2010a7f5aa3d588dc88306dde354 (patch) | |
| tree | ef83694016ce644fe1b9843f126b968f52d613b3 /tests/techmap/dfflegalize_dlatch_init.ys | |
| parent | d3422f8a5e77a472d900f5cdd4066b848839a68f (diff) | |
| parent | 6b42819a37a02ee4cc0724f54cbbd3ac996ca0a8 (diff) | |
| download | yosys-5428666151be2010a7f5aa3d588dc88306dde354.tar.gz yosys-5428666151be2010a7f5aa3d588dc88306dde354.tar.bz2 yosys-5428666151be2010a7f5aa3d588dc88306dde354.zip | |
Merge pull request #2186 from YosysHQ/mwk/dfflegalize
Add dfflegalize pass.
Diffstat (limited to 'tests/techmap/dfflegalize_dlatch_init.ys')
| -rw-r--r-- | tests/techmap/dfflegalize_dlatch_init.ys | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/tests/techmap/dfflegalize_dlatch_init.ys b/tests/techmap/dfflegalize_dlatch_init.ys new file mode 100644 index 000000000..3ec9d9b06 --- /dev/null +++ b/tests/techmap/dfflegalize_dlatch_init.ys @@ -0,0 +1,82 @@ +read_verilog -icells <<EOT + +module dlatch(input E, D, (* init = 2'h0 *) output [1:0] Q); +$_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0])); +$_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ 0 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ 1 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1 + +# Convert everything to DFFs. + +design -load orig +dfflegalize -cell $_DLATCH_P_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_P_ +select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_P_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_P_ +select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i |