diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-02 18:22:43 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-09 18:51:03 +0200 |
| commit | 7ed9d189079135ef53e8a19a5e3a38e240994103 (patch) | |
| tree | e16e3a1c9a3593c62b8ab26e1ba020fdb7542bc8 /tests/techmap/dfflibmap-sim.v | |
| parent | 68babb2ae4cf86e099f28ada45f7e86b37405a4c (diff) | |
| download | yosys-7ed9d189079135ef53e8a19a5e3a38e240994103.tar.gz yosys-7ed9d189079135ef53e8a19a5e3a38e240994103.tar.bz2 yosys-7ed9d189079135ef53e8a19a5e3a38e240994103.zip | |
dfflibmap: Refactor to use dfflegalize internally.
Diffstat (limited to 'tests/techmap/dfflibmap-sim.v')
| -rw-r--r-- | tests/techmap/dfflibmap-sim.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/techmap/dfflibmap-sim.v b/tests/techmap/dfflibmap-sim.v new file mode 100644 index 000000000..1788a683b --- /dev/null +++ b/tests/techmap/dfflibmap-sim.v @@ -0,0 +1,22 @@ +module dffn(input CLK, D, output reg Q, output QN); + +always @(negedge CLK) + Q <= D; + +assign QN = ~Q; + +endmodule + +module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN); + +always @(posedge CLK, posedge CLEAR, posedge PRESET) + if (CLEAR) + Q <= 0; + else if (PRESET) + Q <= 1; + else + Q <= D; + +assign QN = ~Q; + +endmodule |