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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 12:55:03 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 12:55:03 +0100 |
| commit | dcf2e242406d563254013ea7db4b29b55be96eff (patch) | |
| tree | ad242e2b5273a775752a2398171c178df89f9e2a /tests/techmap/mem_simple_4x1_map.v | |
| parent | 913c304fe62cb962e32fa0eb024fa4fc3110639c (diff) | |
| download | yosys-dcf2e242406d563254013ea7db4b29b55be96eff.tar.gz yosys-dcf2e242406d563254013ea7db4b29b55be96eff.tar.bz2 yosys-dcf2e242406d563254013ea7db4b29b55be96eff.zip | |
Added $meminit support to "memory" command
Diffstat (limited to 'tests/techmap/mem_simple_4x1_map.v')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_map.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v index 820f89de4..868f5d00c 100644 --- a/tests/techmap/mem_simple_4x1_map.v +++ b/tests/techmap/mem_simple_4x1_map.v @@ -5,6 +5,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter OFFSET = 0; parameter ABITS = 8; parameter WIDTH = 8; + parameter signed INIT = 1'bx; parameter RD_PORTS = 1; parameter RD_CLK_ENABLE = 1'b1; @@ -37,6 +38,10 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); initial begin _TECHMAP_FAIL_ <= 0; + // no initialized memories + if (INIT !== 1'bx) + _TECHMAP_FAIL_ <= 1; + // only map cells with only one read and one write port if (RD_PORTS > 1 || WR_PORTS > 1) _TECHMAP_FAIL_ <= 1; |