Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 29 insertions, 0 deletions

diff --git a/tests/techmap/mem_simple_4x1_tb.v b/tests/techmap/mem_simple_4x1_tb.v
new file mode 100644
index 000000000..532626960
--- /dev/null
+++ b/tests/techmap/mem_simple_4x1_tb.v
@@ -0,0 +1,29 @@
+module tb;
+
+reg clk, rst;
+wire [7:0] out;
+wire [4:0] counter;
+
+uut uut (clk, rst, out, counter);
+
+initial begin
+	#5 clk <= 0;
+	repeat (100) #5 clk <= ~clk;
+	#5 $finish;
+end
+
+initial begin
+	rst <= 1;
+	repeat (2) @(posedge clk);
+	rst <= 0;
+end
+
+always @(posedge clk)
+	$display("%d %d %d", rst, out, counter);
+
+initial begin
+	$dumpfile("mem_simple_4x1_tb.vcd");
+	$dumpvars(0, uut);
+end
+
+endmodule