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| author | Claire Wolf <clifford@clifford.at> | 2020-03-27 17:28:26 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-27 17:28:26 +0100 |
| commit | 1bf2bdf05bd78a08f932780d99144b2d56e2943f (patch) | |
| tree | b5b237cb924797f58071453165bfeec4f4688656 /tests/techmap/mem_simple_4x1_uut.v | |
| parent | 4c38895fab3ca2426ffc23e40601f3042a953e47 (diff) | |
| parent | c34d7b13f474aec5703884029b553175aeeb2835 (diff) | |
| download | yosys-1bf2bdf05bd78a08f932780d99144b2d56e2943f.tar.gz yosys-1bf2bdf05bd78a08f932780d99144b2d56e2943f.tar.bz2 yosys-1bf2bdf05bd78a08f932780d99144b2d56e2943f.zip | |
Merge pull request #1607 from whitequark/simplify-simplify-meminit
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
Diffstat (limited to 'tests/techmap/mem_simple_4x1_uut.v')
0 files changed, 0 insertions, 0 deletions