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authorSahand Kashani <sahand.kashani@gmail.com>2020-04-08 23:50:37 +0200
committerSahand Kashani <sahand.kashani@gmail.com>2020-04-08 23:50:37 +0200
commit9edf8869c18951ec2b75f074065f073da3253244 (patch)
tree09fba95ba6d3f93ecab828c84b9ff3f74160d7b9 /tests/techmap/techmap_replace.ys
parent820e3d1dad4f484f9646588f79b73b21b495e3d8 (diff)
parent5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff)
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Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
Diffstat (limited to 'tests/techmap/techmap_replace.ys')
-rw-r--r--tests/techmap/techmap_replace.ys18
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index c2f42d50b..8403586bd 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -16,3 +16,21 @@ EOT
techmap -map %techmap
select -assert-any w:s0.asdf
select -assert-any c:s0.blah
+
+read_verilog <<EOT
+module sub(input i, output o, input j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf
+select -assert-any c:s0.blah