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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 13:29:15 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-27 13:29:15 -0800 |
| commit | 48f3f5213eb25237b2e856827a45a9f2baefebe9 (patch) | |
| tree | e6764a9f58b0c51995c2575377749edd4e6c9b14 /tests/techmap | |
| parent | af8281d2f5e3945a8bb93dd7c7400aafb29af3b8 (diff) | |
| parent | 9009b76a69b9e867f69295a8e555305925e83aeb (diff) | |
| download | yosys-48f3f5213eb25237b2e856827a45a9f2baefebe9.tar.gz yosys-48f3f5213eb25237b2e856827a45a9f2baefebe9.tar.bz2 yosys-48f3f5213eb25237b2e856827a45a9f2baefebe9.zip | |
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
Diffstat (limited to 'tests/techmap')
| -rw-r--r-- | tests/techmap/abc9.ys | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index 62b5dfef6..2140dde26 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -39,6 +39,35 @@ design -load gold scratchpad -copy abc9.script.flow3 abc9.script abc9 -lut 4 +design -reset +read_verilog <<EOT +module top(input a, b, output o); +(* keep *) wire w = a & b; +assign o = ~w; +endmodule +EOT + +simplemap +equiv_opt -assert abc9 -lut 4 +design -load postopt +select -assert-count 2 t:$lut + + +design -reset +read_verilog -icells <<EOT +module top(input a, b, output o); +wire w; +(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b)); +assign o = ~w; +endmodule +EOT + +simplemap +equiv_opt -assert abc9 -lut 4 +design -load postopt +select -assert-count 1 t:$lut +select -assert-count 1 t:$_AND_ + design -reset read_verilog -icells <<EOT |