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| author | clairexen <claire@symbioticeda.com> | 2020-08-20 16:23:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-20 16:23:07 +0200 |
| commit | 799076af24ef31e8611bd99180760e7d8cd5a771 (patch) | |
| tree | 7b6e9159b8eb04e9c4ead4739e84293a4a2e5041 /tests/techmap | |
| parent | 6a68b8ed542b89f32303c8036ae0b698d90f8c2b (diff) | |
| parent | c1ed1c28be9bd9880cc036d13f43294bf257788b (diff) | |
| download | yosys-799076af24ef31e8611bd99180760e7d8cd5a771.tar.gz yosys-799076af24ef31e8611bd99180760e7d8cd5a771.tar.bz2 yosys-799076af24ef31e8611bd99180760e7d8cd5a771.zip | |
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed
peeopt.shiftmul: Add a signedness check.
Diffstat (limited to 'tests/techmap')
| -rw-r--r-- | tests/techmap/bug2332.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/techmap/bug2332.ys b/tests/techmap/bug2332.ys new file mode 100644 index 000000000..ed6b35eb2 --- /dev/null +++ b/tests/techmap/bug2332.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [31:0] a, input signed [2:0] x, output [2:0] o); + +wire [5:0] t = x * 3; +assign o = a >> t; + +endmodule +EOT + +wreduce +equiv_opt -assert peepopt |