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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:51:32 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:51:32 -0800 |
commit | 5c89dead5f481edaccd46ebc0af907544c89654f (patch) | |
tree | c40306fef9c52f8065cf5f19b42f31b668b17526 /tests/various/abc9.v | |
parent | 01866a79093092bc2f8a8b20376f6cb552f76f00 (diff) | |
parent | ce765aa4def09bd8b0161425ee40ee55f62e33ff (diff) | |
download | yosys-5c89dead5f481edaccd46ebc0af907544c89654f.tar.gz yosys-5c89dead5f481edaccd46ebc0af907544c89654f.tar.bz2 yosys-5c89dead5f481edaccd46ebc0af907544c89654f.zip |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'tests/various/abc9.v')
-rw-r--r-- | tests/various/abc9.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 30ebd4e26..f0b3f6837 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -9,3 +9,10 @@ wire w; unknown u(~i, w); unknown2 u2(w, o); endmodule + +module abc9_test032(input clk, d, r, output reg q); +initial q = 1'b0; +always @(negedge clk or negedge r) + if (!r) q <= 1'b0; + else q <= d; +endmodule |