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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-11-18 08:19:53 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-11-19 08:57:39 +0100 |
| commit | 15232a48af60fb7da3c3afdd144882ace2194197 (patch) | |
| tree | 9f65f4cf436dd53d1d926ae2bbd85c36433a70ed /tests/various/bug1462.ys | |
| parent | 7a9081440c33af05cd5b24b4eb8907ac2ba4876a (diff) | |
| download | yosys-15232a48af60fb7da3c3afdd144882ace2194197.tar.gz yosys-15232a48af60fb7da3c3afdd144882ace2194197.tar.bz2 yosys-15232a48af60fb7da3c3afdd144882ace2194197.zip | |
Fix #1462, #1480.
Diffstat (limited to 'tests/various/bug1462.ys')
| -rw-r--r-- | tests/various/bug1462.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys new file mode 100644 index 000000000..15cab5121 --- /dev/null +++ b/tests/various/bug1462.ys @@ -0,0 +1,11 @@ +read_verilog << EOF +module top(...); +input wire [31:0] A; +output wire [31:0] P; + +assign P = A * 32'h12300000; + +endmodule +EOF + +synth_xilinx |