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authorEddie Hung <eddie@fpgeh.com>2020-01-28 12:46:18 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-28 12:46:18 -0800
commita855f23f22c9e6dbba5ff17a9541a7d26342b56a (patch)
treef62715ee5a790615d8d4fcda7814a940608c7310 /tests/various/bug1531.ys
parentf5e0a07ad679696b0d3077ef877941d4c1f864d7 (diff)
parent7939727d14f44b5d56ca3806d0907e9fceea2882 (diff)
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Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
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+read_verilog <<EOT
+module top (y, clk, w);
+ output reg y = 1'b0;
+ input clk, w;
+ reg [1:0] i = 2'b00;
+ always @(posedge clk)
+ // If the constant below is set to 2'b00, the correct output is generated.
+ // vvvv
+ for (i = 1'b0; i < 2'b01; i = i + 2'b01)
+ y <= w || i[1:1];
+endmodule
+EOT
+
+synth
+design -stash gate
+
+read_verilog <<EOT
+module gold (y, clk, w);
+ input clk;
+ wire [1:0] i;
+ input w;
+ output y;
+ reg y = 1'h0;
+ always @(posedge clk)
+ y <= w;
+ assign i = 2'h0;
+endmodule
+EOT
+proc gold
+
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -seq 10 -verify -prove-asserts -show-ports miter