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| author | whitequark <whitequark@whitequark.org> | 2021-02-23 21:46:16 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-23 21:46:16 +0000 |
| commit | ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2 (patch) | |
| tree | 7da8cbbf621850924cee90e94d8ad95597f2fa5c /tests/various/const_arg_loop.ys | |
| parent | 4b31223e60f8854d50c1d1bbddca528fbf37d261 (diff) | |
| parent | b6af90fe20bc92631061c48c328f3c6e4760e4df (diff) | |
| download | yosys-ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2.tar.gz yosys-ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2.tar.bz2 yosys-ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2.zip | |
Merge pull request #2594 from zachjs/func-arg-width
verilog: fix sizing of constant args for tasks/functions
Diffstat (limited to 'tests/various/const_arg_loop.ys')
| -rw-r--r-- | tests/various/const_arg_loop.ys | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys index b039bda10..392532213 100644 --- a/tests/various/const_arg_loop.ys +++ b/tests/various/const_arg_loop.ys @@ -1 +1,6 @@ -read_verilog const_arg_loop.v +read_verilog -sv const_arg_loop.sv +hierarchy +proc +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all |