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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-20 15:34:31 -0700 |
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committer | GitHub <noreply@github.com> | 2020-04-20 15:34:31 -0700 |
commit | d32e56a3d1bdb36a77c0c3afad2eb4493292480b (patch) | |
tree | 08ee0263f698739cfeb19476413d5411aa512ab7 /tests/various/dynamic_part_select/reset_test.v | |
parent | e86ba3b94d7285ded20b4280ad52821cbca504fc (diff) | |
parent | caf4071c8bd4494d2c86d3ef9ea7b17fc74bafca (diff) | |
download | yosys-d32e56a3d1bdb36a77c0c3afad2eb4493292480b.tar.gz yosys-d32e56a3d1bdb36a77c0c3afad2eb4493292480b.tar.bz2 yosys-d32e56a3d1bdb36a77c0c3afad2eb4493292480b.zip |
Merge pull request #1975 from dh73/claire/bitselwrite
Adding tests to Claire/bitselwrite branch
Diffstat (limited to 'tests/various/dynamic_part_select/reset_test.v')
-rw-r--r-- | tests/various/dynamic_part_select/reset_test.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/various/dynamic_part_select/reset_test.v b/tests/various/dynamic_part_select/reset_test.v new file mode 100644 index 000000000..29355aafb --- /dev/null +++ b/tests/various/dynamic_part_select/reset_test.v @@ -0,0 +1,23 @@ +module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input clk, + input [CTRLW-1:0] ctrl, + input [DINW-1:0] din, + input [SELW-1:0] sel, + output reg [WIDTH-1:0] dout); + + reg [SELW:0] i; + wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}}; + localparam SLICE = WIDTH/(SELW**2); + // Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for + // whatever reason. + always @(posedge clk) begin + if (reset) begin: reset_mask + for (i = 0; i < {SELW{1'b1}}; i=i+1) begin + dout[i*rval+:SLICE] <= 32'hDEAD; + end + end + //else begin + dout[ctrl*sel+:SLICE] <= din; + //end + end +endmodule |