Merge branch 'master' into xc7dsp

1 files changed, 0 insertions, 223 deletions

diff --git a/tests/various/opt_expr.ys b/tests/various/opt_expr.ys
deleted file mode 100644
index f0306efa1..000000000
--- a/tests/various/opt_expr.ys
+++ /dev/null
@@ -1,223 +0,0 @@
-
-read_verilog <<EOT
-module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = (i << 4) + j;
-endmodule
-EOT
-
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-# alumacc version of above
-design -reset
-read_verilog <<EOT
-module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = (i << 4) + j;
-endmodule
-EOT
-
-alumacc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-design -reset
-read_verilog <<EOT
-module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
-    assign o = (i << 4) + j;
-endmodule
-EOT
-
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-# alumacc version of above
-design -reset
-read_verilog <<EOT
-module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
-    assign o = (i << 4) + j;
-endmodule
-EOT
-
-alumacc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-design -reset
-read_verilog <<EOT
-module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = j - (i << 4);
-endmodule
-EOT
-
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-# alumacc version of above
-design -reset
-read_verilog <<EOT
-module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = j - (i << 4);
-endmodule
-EOT
-
-alumacc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-dump
-select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-design -reset
-read_verilog <<EOT
-module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
-    assign o = j - (i << 4);
-endmodule
-EOT
-
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-# alumacc version of above
-design -reset
-read_verilog <<EOT
-module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
-    assign o = j - (i << 4);
-endmodule
-EOT
-
-alumacc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-design -reset
-read_verilog <<EOT
-module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = (i << 4) - j;
-endmodule
-EOT
-
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
-
-##########
-
-# alumacc version of above
-design -reset
-read_verilog <<EOT
-module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = (i << 4) - j;
-endmodule
-EOT
-
-alumacc
-opt_expr -fine
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
-
-##########
-
-design -reset
-read_verilog <<EOT
-module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
-    assign o = 5'b00010 - i;
-endmodule
-EOT
-
-wreduce
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-##########
-
-# alumacc version of above
-design -reset
-read_verilog <<EOT
-module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
-    assign o = 5'b00010 - i;
-endmodule
-EOT
-
-wreduce
-alumacc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-###########
-
-design -reset
-read_verilog -icells <<EOT
-module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
-    \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
-endmodule
-EOT
-check
-
-equiv_opt -assert opt_expr -fine
-design -load postopt
-select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-###########
-
-design -reset
-read_verilog -icells <<EOT
-module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
-    \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
-endmodule
-EOT
-check
-
-equiv_opt opt_expr -fine
-design -load postopt
-select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-###########
-
-design -reset
-read_verilog -icells <<EOT
-module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
-    \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
-endmodule
-EOT
-check
-
-equiv_opt opt_expr -fine
-design -load postopt
-select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i