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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:44:21 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:44:21 -0700 |
| commit | 6c2cb519965ac9b4057a90cd46f474c092967be2 (patch) | |
| tree | 45f545af7700a244f64a0e42f96fae37df9f2914 /tests/various/shregmap.ys | |
| parent | 301e065aeee2d6a4b5009ebdc50028bafd3aac5d (diff) | |
| parent | 1abe93e48d8bb78cd0753d46dfbe1885a1e803eb (diff) | |
| download | yosys-6c2cb519965ac9b4057a90cd46f474c092967be2.tar.gz yosys-6c2cb519965ac9b4057a90cd46f474c092967be2.tar.bz2 yosys-6c2cb519965ac9b4057a90cd46f474c092967be2.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'tests/various/shregmap.ys')
| -rw-r--r-- | tests/various/shregmap.ys | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys new file mode 100644 index 000000000..d644a88aa --- /dev/null +++ b/tests/various/shregmap.ys @@ -0,0 +1,66 @@ +read_verilog shregmap.v +design -save read + +design -copy-to model $__SHREG_DFF_P_ +hierarchy -top shregmap_static_test +prep +design -save gold + +techmap +shregmap -init + +opt + +stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__SHREG_DFF_P_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +design -load gold +stat + +design -load gate +stat + +########## + +design -load read +design -copy-to model $__XILINX_SHREG_ +hierarchy -top shregmap_variable_test +prep +design -save gold + +simplemap t:$dff t:$dffe +shregmap -tech xilinx + +stat +# show -width +write_verilog -noexpr -norename +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +design -load gold +stat + +design -load gate +stat |