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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 12:43:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 12:43:02 -0700 |
| commit | 3839bd50f28a16f1253a56d5871465763e72180c (patch) | |
| tree | a13a5da510880cdb41061dbe114323778f5f2ea8 /tests/various | |
| parent | 25ff27e37fcb12c6a298267eda2464431304d713 (diff) | |
| download | yosys-3839bd50f28a16f1253a56d5871465763e72180c.tar.gz yosys-3839bd50f28a16f1253a56d5871465763e72180c.tar.bz2 yosys-3839bd50f28a16f1253a56d5871465763e72180c.zip | |
Add test
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/wreduce.ys | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys new file mode 100644 index 000000000..0b5403fa1 --- /dev/null +++ b/tests/various/wreduce.ys @@ -0,0 +1,22 @@ + +read_verilog <<EOT +module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o); + assign o = (i << 4) + j; +endmodule +EOT + +hierarchy -top wreduce_add_test +proc +design -save gold + +prep + +select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 %i %i + +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter |