diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 13:29:15 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-27 13:29:15 -0800 |
| commit | 48f3f5213eb25237b2e856827a45a9f2baefebe9 (patch) | |
| tree | e6764a9f58b0c51995c2575377749edd4e6c9b14 /tests/various | |
| parent | af8281d2f5e3945a8bb93dd7c7400aafb29af3b8 (diff) | |
| parent | 9009b76a69b9e867f69295a8e555305925e83aeb (diff) | |
| download | yosys-48f3f5213eb25237b2e856827a45a9f2baefebe9.tar.gz yosys-48f3f5213eb25237b2e856827a45a9f2baefebe9.tar.bz2 yosys-48f3f5213eb25237b2e856827a45a9f2baefebe9.zip | |
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/abc9.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 81d0afd1b..0c7695089 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -14,6 +14,7 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + design -load read hierarchy -top abc9_test028 proc @@ -23,6 +24,7 @@ select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i select -assert-count 1 t:unknown select -assert-none t:$lut t:unknown %% t: %D + design -load read hierarchy -top abc9_test032 proc @@ -38,3 +40,16 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -seq 10 -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog -icells <<EOT +module abc9_test036(input clk, d, output q); +(* keep *) reg w; +$__ABC9_FF_ ff(.D(d), .Q(w)); +wire \ff.clock = clk; +wire \ff.init = 1'b0; +assign q = w; +endmodule +EOT +abc9 -lut 4 -dff |