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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 00:48:22 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 00:48:22 -0800 |
| commit | 8c813632b6c1557f5123ea0cece2738fad40b89b (patch) | |
| tree | 629e014e6e5fa25c1615b36876110acfbe42d48c /tests/various | |
| parent | 969f51141535ac70d8fbb2a0e2da7ee2aba833b8 (diff) | |
| download | yosys-8c813632b6c1557f5123ea0cece2738fad40b89b.tar.gz yosys-8c813632b6c1557f5123ea0cece2738fad40b89b.tar.bz2 yosys-8c813632b6c1557f5123ea0cece2738fad40b89b.zip | |
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45.
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/submod.ys | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index a0a3f2da5..552fd4e01 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -52,8 +52,10 @@ sat -verify -prove-asserts -show-ports miter design -reset read_verilog -icells <<EOT -module top(input d, c, (* init = 1'b1 *) output reg q); -(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q)); +module top(input d, c, (* init = 3'b011 *) output reg [2:0] q); +(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); +DFF s2(.D(d), .C(c), .Q(q[0])); +DFF s3(.D(d), .C(c), .Q(q[2])); endmodule module DFF(input D, C, output Q); @@ -62,6 +64,7 @@ endmodule EOT hierarchy -top top +proc submod dffinit -ff DFF Q INIT |