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author | George Rennie <georgerennie@gmail.com> | 2021-12-23 01:10:32 +0000 |
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committer | George Rennie <georgerennie@gmail.com> | 2022-06-24 00:17:02 +0100 |
commit | fbf5d89587decd2886d501d8c6e1cde076a5476f (patch) | |
tree | b2dd44a7240e6c03d4450aef89f45015c3850589 /tests/various | |
parent | 34804f3fb63d8f576ec614904171c1384839cd73 (diff) | |
download | yosys-fbf5d89587decd2886d501d8c6e1cde076a5476f.tar.gz yosys-fbf5d89587decd2886d501d8c6e1cde076a5476f.tar.bz2 yosys-fbf5d89587decd2886d501d8c6e1cde076a5476f.zip |
equiv_make: Add -make_assert option
This adds a -make_assert flag to equiv_make. When used, the pass generates
$eqx and $assert cells to encode equivalence instead of $equiv.
Diffstat (limited to 'tests/various')
-rw-r--r-- | tests/various/equiv_make_make_assert.ys | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/tests/various/equiv_make_make_assert.ys b/tests/various/equiv_make_make_assert.ys new file mode 100644 index 000000000..1c2efa723 --- /dev/null +++ b/tests/various/equiv_make_make_assert.ys @@ -0,0 +1,32 @@ +read_verilog <<EOT +module gold( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] c +); + +wire [7:0] b_neg; +assign b_neg = -b; +assign c = a + b_neg; +endmodule + +module gate( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] c +); + +wire [7:0] b_neg; +assign b_neg = ~b + 1; +assign c = a + b_neg; +endmodule + +EOT + +equiv_make -make_assert gold gate miter + +select -assert-count 0 t:$equiv +select -assert-count 2 t:$assert + +prep -top miter +sat -prove-asserts -verify |