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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-30 01:15:49 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-30 02:29:26 +0200 |
| commit | 0505c604e70c6d9621eb6ace6a9d8a3a5ac71eaa (patch) | |
| tree | 3a42f43d13d549df7b4b1eba52e2871948de4cb8 /tests/verilog/absurd_width_const.ys | |
| parent | 1af994802ed75d5805191113f669409c3872fcf7 (diff) | |
| download | yosys-0505c604e70c6d9621eb6ace6a9d8a3a5ac71eaa.tar.gz yosys-0505c604e70c6d9621eb6ace6a9d8a3a5ac71eaa.tar.bz2 yosys-0505c604e70c6d9621eb6ace6a9d8a3a5ac71eaa.zip | |
preproc: Fix up conditional handling.
Fixes #2710.
Fixes #2711.
Diffstat (limited to 'tests/verilog/absurd_width_const.ys')
0 files changed, 0 insertions, 0 deletions